Publications

Journal & Conference Papers

Peer-reviewed publications in IEEE journals, international conferences, and open-access venues. Sorted by date (newest first).

2026
1

Advancing Non-Faradaic Impedance Biosensors: Sensitivity Enhancement Strategies Using Microfluidics, Multiscale Labeling, and CMOS Technology Microsyst. Nanoeng.

N.-S. Kim, J. Kim
Microsystems & Nanoengineering (Springer Nature), 2026
2

Parasitic-Aware Design of a 0.4–6-GHz Quadrature LO Generator in 14-nm FinFET IEEE TVLSI

N.-S. Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2026
2025
3

A Physics-Based Compact Model for Multibit SR-RRAM Driven by Alkali Ion Migration and Interfacial Barrier Modulation IEEE TED

J.S. Beom, N.-S. Kim
IEEE Transactions on Electron Devices, 2025
4

CMOS Impedance Sensor with 128×128 Microelectrode Arrays for Measuring Surface Coverage of Microparticles IEEE SENSORS

H. Shin, D. Kang, J. Kim, N.-S. Kim
2025 IEEE SENSORS, pp. 1–4
5

Resonator Width Optimization for Enhanced Performance and Bonding Reliability in Wideband RF MEMS Filter Micromachines

G. Jeon, M. Jeong, S. Lee, Y. Jo, N.-S. Kim
Micromachines, vol. 16, no. 8, p. 878, 2025
6

A Low-Power Complementary Metal-Oxide-Semiconductor Receiver with Quadrature Bandpass Continuous-Time Delta–Sigma Analog-to-Digital Converter for IoT Applications Sensors

N.-S. Kim
Sensors, vol. 25, no. 6, p. 1748, 2025
2024
7

An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications Sensors

N.-S. Kim
Sensors, vol. 24, no. 16, p. 5255, 2024
8

A 2.4 GHz Wide-Range CMOS Current-Mode Class-D PA with HD2 Suppression for Internet of Things Applications Sensors

N.-S. Kim
Sensors, vol. 24, no. 5, p. 1616, 2024
9

A Compact Model for Interface-Type Self-Rectifying Resistive Memory with Experiment Verification IEEE Access

J.W. Kim, J.S. Beom, H.S. Lee, N.-S. Kim
IEEE Access, vol. 12, pp. 5081–5091, 2024
2022
10

A 10-Bit, 600 MS/s Multi-Mode Direct-Sampling DAC-Based Transmitter IEEE Access

N.-S. Kim
IEEE Access, vol. 10, pp. 125696–125706, 2022
2021
11

A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT IEEE TVLSI

J. Choi, N.-S. Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 12, 2021
2020
12

A Digital-Intensive Extended-Range Dual-Mode BLE5.0 and IEEE802.15.4 Transceiver SoC IEEE TMTT

N.-S. Kim
IEEE Transactions on Microwave Theory and Techniques, 2020
2019
13

A 1.04–4V, Digital-Intensive Dual-Mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with Extended Range in 28nm CMOS IEEE RFIC

N.-S. Kim, M.-G. Kim, A. Verma, G. Seol, S. Kim, S. Lee, C. Lo, J. Han, I. Jo, C. Kim, C.-W. Yao, J. Lee
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019
14

A 0.46–2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOS IEEE A-SSCC

J. Choi, N.-S. Kim, J. Han, T.B. Cho
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)
2018
15

A 3.1–10.6-GHz 57-Bands CMOS Frequency Synthesizer for UWB-Based Cognitive Radios IEEE TMTT

N.-S. Kim, J.M. Rabaey
IEEE Transactions on Microwave Theory and Techniques, 2018
16

A Dual-Resolution Wavelet-Based Energy Detection Spectrum Sensing for UWB-Based Cognitive Radios IEEE TCAS-I

N.-S. Kim, J.M. Rabaey
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
17

A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration IEEE JSSC

C.-W. Yao, W.F. Loke, R. Ni, Y. Han, H. Li, K. Godbole, Y. Zuo, S. Ko, N.-S. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S.W. Son, T.B. Cho
IEEE Journal of Solid-State Circuits, vol. 53, no. 1, 2018
2017
18

A 14nm Fractional-N Digital PLL with 0.14psrms Jitter and −78dBc Fractional Spur for Cellular RFICs IEEE ISSCC

C.-W. Yao, W.F. Loke, R. Ni, Y. Han, H. Li, K. Godbole, Y. Zuo, S. Ko, N.-S. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S.W. Son, T.B. Cho
IEEE International Solid-State Circuits Conference (ISSCC), 2017
2016
19

A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio IEEE JSSC

N.-S. Kim, J.M. Rabaey
IEEE Journal of Solid-State Circuits, 2016
2015
20

A 3.1–10.6 GHz Wavelet-Based Dual-Resolution Spectrum Sensing with Harmonic Rejection Mixers IEEE ESSCIRC

N.-S. Kim, J.M. Rabaey
IEEE European Solid-State Circuits Conference (ESSCIRC), 2015
21

A 1Gb/s Energy Efficient Triple-Channel UWB-Based Cognitive Radio VLSI Circuits

N.-S. Kim, J.M. Rabaey
2015 Symposium on VLSI Circuits (VLSI Circuits)
22

A 3–10mW, 3.1–10.6 GHz Integer-N QPLL with Reference Spur Reduction Technique for UWB-Based Cognitive Radios IEEE RFIC

N.-S. Kim, J.M. Rabaey
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
2014
23

Denoising Traffic Collision Data Using Ensemble Empirical Mode Decomposition (EEMD) and Its Application for Constructing Continuous Risk Profile (CRP) Accident Analysis

N.-S. Kim, K. Chung, S. Ahn, J.W. Yu, K. Choi
Accident Analysis & Prevention, 2014
24

Denoising Traffic Collision Data Using Ensemble Empirical Mode Decomposition and Its Application for Constructing Continuous Risk Profile TRB

N.-S. Kim, K. Chung, S. Ahn, J.W. Yu, K. Choi
Transportation Research Board Annual Meeting, 2014
2013
25

A 0.2 to 1.7 GHz Low-Jitter Integer-N QPLL for Power Efficient Direct Digital RF Modulator IEEE A-SSCC

N.-S. Kim, J.M. Rabaey
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
2011
26

A 10b 600MS/s Multi-Mode CMOS DAC for Multiple Nyquist Zone Operation VLSI Circuits

S.Y.-S. Chen, N.-S. Kim, J. Rabaey
2011 Symposium on VLSI Circuits — Digest of Technical Papers
2008
27

Multi-Mode Sub-Nyquist Rate Digital-to-Analog Conversion for Direct Waveform Synthesis IEEE SiPS

S.Y.-S. Chen, N.-S. Kim, J.M. Rabaey
2008 IEEE Workshop on Signal Processing Systems
Earlier
28

A Phase-Locked Loop with Reference Clock-Based Locking Time for Above-2.0 Gb/s/pin DRAM Interface ISOCC

H.-J. Yang, K.-I. Park, N.-S. Kim, J.-S. Kim, J.-W. Kim, B.-S. Kong, J.-S. Choi, Y.-H. Jun
ISOCC 2007 Conference
29

A SRAM Core Architecture with Adaptive Cell Bias Scheme VLSI Circuits

H.-S. Yu, N.-S. Kim, Y.-J. Son, Y.-G. Kim, H.-C. Kim, U.-R. Cho
2006 Symposium on VLSI Circuits, Digest of Technical Papers
30

SMD-Based Internal Clock Generator for Memory Test ISOCC

H.-C. Kim, N.-S. Kim, H.-S. Yu, U.-R. Cho, H.-G. Byun
ISOCC 2005 Conference
31

Low Voltage Wide Range DLL-Based Quad-Phase Core Clock Generator for High Speed Network SRAM Application IEEE CICC

N.-S. Kim, U.-R. Cho, H.-G. Byun
IEEE Custom Integrated Circuits Conference (CICC), 2005
32

A Pseudo-Differential CMOS Receiver Insensitive to Input Common Mode Level IEEE ISCAS

N.-S. Kim, U.-R. Cho, H.-G. Byun
2005 IEEE International Symposium on Circuits and Systems (ISCAS)
33

Synchronous Mirror Delay for Multiphase Locking IEEE JSSC

Y.J. Yoon, H.I. Kwon, J.D. Lee, B.G. Park, N.-S. Kim, U.R. Cho
IEEE Journal of Solid-State Circuits
34

Programmable and Automatically Adjustable On-Die Terminator for DDR3-SRAM Interface IEEE CICC

N.-S. Kim, Y.-J. Yoon, U.-R. Cho, H.-G. Byun
IEEE Custom Integrated Circuits Conference (CICC), 2004
35

New Dynamic Logic-Level Converters for High Performance Application IEEE ISCAS

N.-S. Kim, Y.-J. Yoon, U.-R. Cho, H.-G. Byun
IEEE International Symposium on Circuits and Systems (ISCAS), 2003
36

A 1.2 V 1.5 Gb/s 72Mb DDR3 SRAM IEEE JSSC

U.-R. Cho, T.-H. Kim, Y.-J. Yoon, J.-C. Lee, D.-G. Bae, N.-S. Kim, K.-Y. Kim, Y.-J. Son, J.-S. Yang, K.-I. Sohn, S.-T. Kim, I.-Y. Lee, K.-J. Lee, T.-G. Kang, S.-C. Kim, K.-S. Ahn, H.-G. Byun
IEEE Journal of Solid-State Circuits, 2004
37

A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM IEEE ISSCC

U.-R. Cho, T.-H. Kim, Y.-J. Yoon, J.-C. Lee, D.-G. Bae, N.-S. Kim, K.-Y. Kim, Y.-J. Son, J.-S. Yang, K.-I. Sohn, S.-T. Kim, I.-Y. Lee, K.-J. Lee, T.-G. Kang, S.-C. Kim, K.-S. Ahn, H.-G. Byun
IEEE International Solid-State Circuits Conference (ISSCC), 2004
38

Programmable Digital On-Chip Terminator ITC-CSCC

S.-C. Kim, N.-S. Kim, T.-H. Kim, U.-R. Cho, H.-G. Byun, S. Kim
ITC-CSCC: 2002 Proceedings
39

Fabrication of Silicon Field Emitter Arrays Combined with HVTFT at Low Temperature JKPS

J.D. Lee, N.-S. Kim, I.H. Kim, B.-G. Park
Journal of the Korean Physical Society, 1998
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IP

US Patents

Granted United States patents. Sorted by issue date (newest first).

2021
1

Integrated Circuit with Adaptability to a Process-Voltage-Temperature (PVT) Variation US11086345B2

Issued 2021
2020
2

Integrated Circuit with Adaptability to a Process-Voltage-Temperature (PVT) Variation US10747250B2

Issued 2020
3

Wide-Range Local Oscillator (LO) Generators and Apparatuses Including the Same US10715159B2

Issued 2020
2019
4

Frequency Divider and a Transceiver Including the Same US10547315B2

Issued 2019
5

Wide-Range Local Oscillator (LO) Generators and Apparatuses Including the Same US10326460B2

Issued 2019
2018
6

Digital-to-Time Converter and Operating Method Thereof US10122378B2

Issued 2018
2010
7

Delay-Locked Loop Circuits and Method for Generating Transmission Core Clock Signals US7825710B2

Issued 2010
8

Data Line Layout and Line Driving Method in Semiconductor Memory Device US7697314B2

Issued 2010
9

Semiconductor Memory Device with Hierarchical Bit Line Structure US7656723B2

Issued 2010
2009
10

Semiconductor Memory Device with Hierarchical Bit Line Structure US7616512B2

Issued 2009
11

Phase Interpolation Circuit and Method of Generating Phase Interpolation Signal US7551013B2

Issued 2009
12

Semiconductor Memory Device with Hierarchical Bit Line Structure US7489570B2

Issued 2009
2008
13

Amplifier Circuit Having Constant Output Swing Range and Stable Delay Time US7400177B2

Issued 2008
2007
14

Programmable Impedance Controller and Method for Operating US7288966B2

Issued 2007
15

Amplifier Circuit Having Constant Output Swing Range and Stable Delay Time US7187214B2

Issued 2007
16

Impedance Controller and Impedance Control Method US7170318B2

Issued 2007
2006
17

Apparatus for Generating Internal Clock Signal US7154312B2

Issued 2006
18

Semiconductor Memory Device Capable of Generating Variable Clock Signals According to Modes of Operation US7016257B2

Issued 2006
19

Synchronous Mirror Delay Circuit and Semiconductor Integrated Circuit Device Having the Same US6992514B2

Issued 2006
2005
20

Semiconductor Device with Impedance Control Circuit US6947336B2

Issued 2005
21

Integrated Circuit with On-Chip Termination US6930508B2

Issued 2005
2004
22

Method of Outputting Internal Information Through Test Pin of Semiconductor Memory and Output Circuit Thereof US6834366B2

Issued 2004
2003
23

Programmable Impedance Control Circuit US6661250B2

Issued 2003
24

Programmable Termination Circuit and Method US6642740B2

Issued 2003
25

Impedance Control Circuit US6573746B2

Issued 2003
26

Impedance Updating Apparatus of Termination Circuit and Impedance Updating Method Thereof US6556038B2

Issued 2003
27

Programmable Impedance Control Circuit US6525558B2

Issued 2003
28

Delay Circuit Using Current Source US6509774B2

Issued 2003
2002
29

Programmable Impedance Control Circuit and Method Thereof US6429679B1

Issued 2002